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MOTOROLA
Freescale Semiconductor, Inc.
SEMICONDUCTOR TECHNICAL DATA
Order Number: MPC9653/D Rev 3, 02/2003
3.3V 1:8 LVCMOS PLL Clock Generator
The MPC9653 is a 3.3V compatible, 1:8 PLL based clock generator and zero-delay buffer targeted for high performance low-skew clock distribution in mid-range to high-performance telecom, networking and computing applications. With output frequencies up to 125 MHz and output skews less than 150 ps the device meets the needs of the most demanding clock applications. Features * 1:8 PLL based low-voltage clock generator
MPC9653
LOW VOLTAGE 3.3V LVCMOS 1:8 PLL CLOCK GENERATOR
Freescale Semiconductor, Inc...
Pin and function compatible to the MPC953 FA SUFFIX Functional Description 32 LEAD LQFP PACKAGE The MPC9653 utilizes PLL technology to frequency lock its outputs CASE 873A onto an input reference clock. Normal operation of the MPC9653 requires the connection of the QFB output to the feedback input to close the PLL feedback path (external feedback). With the PLL locked, the output frequency is equal to the reference frequency of the device and VCO_SEL selects the operating frequency range of 25 to 62.5 MHz or 50 to 125 MHz. The two available post-PLL dividers selected by VCO_SEL (divide-by-4 or divide-by-8) and the reference clock frequency determine the VCO frequency. Both must be selected to match the VCO frequency range. The internal VCO of the MPC9653 is running at either 4x or 8x of the reference clock frequency. The MPC9653 has a differential LVPECL reference input along with an external feedback input. The device is ideal for use as a zero delay, low skew fanout buffer. The device performance has been tuned and optimized for zero delay performance. The PLL_EN and BYPASS controls select the PLL bypass configuration for test and diagnosis. In this configuration, the selected input reference clock is bypassing the PLL and routed either to the output dividers or directly to the outputs. The PLL bypass configurations are fully static and the minimum clock frequency specification and all other PLL characteristics do not apply. The outputs can be disabled (high-impedance) and the device reset by asserting the MR/OE pin. Asserting MR/OE also causes the PLL to loose lock due to missing feedback signal presence at FB_IN. Deasserting MR/OE will enable the outputs and close the phase locked loop, enabling the PLL to recover to normal operation. The MPC9653 is fully 3.3V compatible and requires no external loop filter components. The inputs (except PCLK) accept LVCMOS except signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 transmission lines. For series terminated transmission lines, each of the MPC9653 outputs can drive one or two traces giving the devices an effective fanout of 1:16. The device is packaged in a 7x7 mm2 32-lead LQFP package.
* * * * * * * * * *
Supports zero-delay operation 3.3V power supply Generates clock signals up to 125 MHz Maximum output skew of 150 ps Differential LVPECL reference clock input External PLL feedback Drives up to 16 clock lines 32 lead LQFP packaging Ambient temperature range 0C to +70C
W
(c) Motorola, Inc. 2003
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MPC9653
VCC 225k PCLK PCLK 0
&
Q0 /1 /2 0 0 1 /4 Q1 1 Q2 Q3 Q4 Q5
Ref
VCO
1
PLL 200-500 MHz VCC 25k FB_IN VCC 325k PLL_EN FB
Q6 Q7 QFB
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VCO_SEL BYPASS MR/OE 25k
Figure 1. MPC9653 Logic Diagram
GND
24 GND Q0 VCC QFB GND PLL_EN BYPASS VCO_SEL 25 26 27 28
23
22
21
20
19
18
17 16 15 14 13 Q5 VCC Q6 GND Q7 VCC MR/OE PCLK
MPC9653
29 30 31 32 1 2 3 4 5 6 7 8 12 11 10 9
VCC_PLL
Figure 2. MPC9653 32-Lead Package Pinout (Top View)
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FB_IN
PCLK
GND
NC
NC
NC
NC
GND
VCC
VCC
Q1
Q2
Q3
Q4
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MPC9653
Table 1: PIN CONFIGURATION
Pin PCLK, PCLK FB_IN VCO_SEL BYPASS PLL_EN MR/OE Q0-7 QFB GND VCC_PLL I/O Input Input Input Input Input Input Output Output Supply Supply Supply Type LVPECL LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS Ground VCC VCC PECL reference clock signal PLL feedback signal input, connect to QFB Operating frequency range select PLL and output divider bypass select PLL enable/disable Output enable/disable (high-impedance tristate) and device reset Clock outputs Clock output for PLL feedback, connect to FB_IN Negative power supply (GND) PLL positive power supply (analog power supply). It is recommended to use an external RC filter for the analog power supply pin VCC_PLL. Please see applications section for details. Positive power supply for I/O and core. All VCC pins must be connected to the positive power supply for correct operation Function
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VCC
Table 2: FUNCTION TABLE
Control PLL_EN Default 1 0 Test mode with PLL bypassed. The reference clock (PCLK) is substituted for the internal VCO output. MPC9653 is fully static and no minimum frequency limit applies. All PLL related AC characteristics are not applicable. Test mode with PLL and output dividers bypassed. The reference clock (PCLK) is directly routed to the outputs. MPC9653 is fully static and no minimum frequency limit applies. All PLL related AC characteristics are not applicable. VCO / 1 (High frequency range). fREF = fQ0-7 = 4 fVCO Outputs enabled (active) Selects the VCO outputa 1
BYPASS
1
Selects the output dividers.
VCO_SEL MR/OE
1 0
VCO / 2 (Low output range). fREF = fQ0-7 = 8 fVCO Outputs disabled (high-impedance state) and reset of the device. During reset the PLL feedback loop is open. The VCO is tied to its lowest frequency. The length of the reset pulse should be greater than one reference clock cycle (PCLK).
a. PLL operation requires BYPASS=1 and PLL_EN=1.
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MPC9653
Table 3: GENERAL SPECIFICATIONS
Symbol VTT MM HBM LU CPD CIN Characteristics Output Termination Voltage ESD Protection (Machine Model) ESD Protection (Human Body Model) Latch-Up Immunity Power Dissipation Capacitance Input Capacitance 200 2000 200 10 4.0 Min Typ VCC
B2
Max
Unit V V V mA pF pF
Condition
Per output Inputs
Table 4: ABSOLUTE MAXIMUM RATINGSa
Symbol VCC VIN Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Characteristics Min -0.3 -0.3 -0.3 Max 3.9 VCC+0.3 VCC+0.3 20 50 Unit V V V mA mA Condition
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VOUT IIN IOUT
TS Storage Temperature -65 125 C a. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied.
Table 5: DC CHARACTERISTICS (VCC = 3.3V 5%, TA = 0C to 70C)
Symbol VIH VIL VPP VCMRa VOH VOL ZOUT IIN ICC_PLL ICCQd Characteristics Input high voltage Input low voltage Peak-to-peak input voltage Common Mode Range Output High Voltage Output Low Voltage Output impedance Input Currentc Maximum PLL Supply Current 14 - 17 200 5.0 10 (PCLK) (PCLK) 300 1.0 2.4 0.55 0.30 VCC-0.6 Min 2.0 Typ Max VCC + 0.3 0.8 Unit V V mV V V V V Condition LVCMOS LVCMOS LVPECL LVPECL IOH=-24 mAb IOL= 24 mA IOL= 12 mA VIN=VCC or GND VCC_PLL Pin
W
A mA
Maximum Quiescent Supply Current 10 mA All VCC Pins a VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (DC) specification. b The MPC9653 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines. The MPC9653 meets the VOH and VOL specification of the MPC953 (VOH > VCC-0.6V at IOH=-20mA and VOL > 0.6V at IOL=20mA). c Inputs have pull-down or pull-up resistors affecting the input current. d OE/MR=1 (outputs in high-impedance state).
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MPC9653
Table 6: AC CHARACTERISTICS (VCC = 3.3V 5%, TA = 0C to 70C)a
Symbol fREF Characteristics Input reference frequency PLL mode, external feedback /4 feedbackb /8 feedbackc Min 50 25 0 200 50 25 450 1.2 2 PCLK to FB_IN -75 1.2 3.0 125 3.3 7.0 150 1.5 45 0.1 50 55 1.0 7.0 6.0 100 100 RMS (1 ) / 4 feedbackb / 8 feedbackc 25 0.8 - 4 0.5 - 1.3 Typ Max 125 62.5 200 500 125 62.5 1000 VCC-0.75 Unit MHz MHz MHz MHz MHz MHz mV V ns ps ns ns ps ns % ns ns ns ps ps ps MHz MHz BYPASS=0 PLL locked 0.55 to 2.4V PLL locked PLL locked PLL locked LVPECL LVPECL Condition PLL locked PLL locked
fVCO fMAX VPP VCMRf tPW,MIN t() tPD
Input reference frequency in PLL bypass moded VCO lock frequency rangee Output Frequency Peak-to-peak input voltage Common Mode Range Input Reference Pulse Widthg Propagation Delay (static phase offset)h Propagation Delay PLL and divider bypass (BYPASS=0), PCLK to Q0-7 PLL disable (BYPASS=1 and PLL_EN=0), PCLK to Q0-7 Output-to-output Skewi Device-to-device Skew in PLL and divider bypassj Output duty cycle Output Rise/Fall Time Output Disable Time Output Enable Time Cycle-to-cycle jitter Period Jitter I/O Phase Jitterk PLL closed loop bandwidthl PLL mode, external feedback /4 feedbackb /8 feedbackc PCLK PCLK
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tsk(O) tsk(PP) DC tR, tF tPLZ, HZ tPZL, LZ tJIT(CC) tJIT(PER) tJIT() BW
tLOCK Maximum PLL Lock Time 10 ms AC characteristics apply for parallel output termination of 50 to VTT. /4 PLL feedback (high frequency range) requires VCO_SEL=0, PLL_EN=1, BYPASS=1 and MR/OE=0. /8 PLL feedback (low frequency range) requires VCO_SEL=1, PLL_EN=1, BYPASS=1 and MR/OE=0. In bypass mode, the MPC9653 divides the input reference clock. The input frequency fREF must match the VCO frequency range divided by the feedback divider ratio FB: fREF = fVCO / FB. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t(). g Calculation of reference duty cycle limits: DCREF,MIN = tPW,MIN fREF 100% and DCREF,MAX = 100% - DCREF,MIN. E.g. at fREF=100 MHz the input duty cycle range is 20% < DC < 80%. h Valid for fREF=50 MHz and FB=/8 (VCO_SEL=1). For other reference frequencies: t() [ps] = 50 ps (1/(120 fREF)). i See application section for part-to-part skew calculation in PLL zero-delay mode. j For a specified temperature and voltage, includes output skew. k I/O phase jitter is reference frequency dependent. See application section for details. l -3 dB point of PLL transfer characteristics. a b c d e f
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Freescale Semiconductor, Inc.
MPC9653
APPLICATIONS INFORMATION
Programming the MPC9653 The MPC9653 supports output clock frequencies from 25 to 125 MHz. Two different feedback divider configurations can be used to achieve the desired frequency operation range. The feedback divider (VCO_SEL) should be used to situate the VCO in the frequency lock range between 200 and Table 9: MPC9653 Configurations (QFB connected to FB_IN)
BYPASS 0 1 PLL_EN X 0 0 1 1 VCO_SEL X 0 1 0 1 Operation Ratio Test mode: PLL and divider bypass Test mode: PLL bypass Test mode: PLL bypass PLL mode (high frequency range) PLL mode (low frequency range) fQ0-7 = fREF fQ0-7 = fREF / 4 fQ0-7 = fREF / 8 fQ0-7 = fREF fQ0-7 = fREF Frequency Output range (fQ0-7) 0-200 MHz 0-50 MHz 0-25 MHz 50 to 125 MHz 25 to 62.5 MHz VCO n/a n/a n/a fVCO = fREF 4 fVCO = fREF 8
500 MHz for stable and optimal operation. Two operating frequency ranges are supported: 25 to 62.5 MHz and 50 to 125 MHz. Table 9 illustrates the configurations supported by the MPC9653. PLL zero-delay is supported if BYPASS=1, PLL_EN=1 and the input frequency is within the specified PLL reference frequency range.
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1 1 1
Power Supply Filtering The MPC9653 is a mixed analog/digital product. Its analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. Random noise on the VCCA_PLL power supply impacts the device characteristics, for instance I/O jitter. The MPC9653 provides separate power supplies for the output buffers (VCC) and the phase-locked loop (VCCA_PLL) of the device. The purpose of this design technique is to isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. The simple but effective form of isolation is a power supply filter on the VCC_PLL pin for the MPC9653. Figure 3. illustrates a typical power supply filter scheme. The MPC9653 frequency and phase stability is most susceptible to noise with spectral content in the 100kHz to 20MHz range. Therefore the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop across the series filter resistor RF. From the data sheet the ICCA current (the current sourced through the VCC_PLL pin) is typically 5 mA (10 mA maximum), assuming that a minimum of 2.985V must be maintained on the VCC_PLL pin.
RF = 5-15 RF VCC CF 10 nF CF = 22 F VCC_PLL MPC9653 VCC 33...100 nF
The minimum values for RF and the filter capacitor CF are defined by the required filter characteristics: the RC filter should provide an attenuation greater than 40 dB for noise whose spectral content is above 100 kHz. In the example RC filter shown in Figure 3. "VCC_PLL Power Supply Filter", the filter cut-off frequency is around 4 kHz and the noise attenuation at 100 kHz is better than 42 dB. As the noise frequency crosses the series resonant point of an individual capacitor its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. Although the MPC9653 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL) there still may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs. Using the MPC9653 in zero-delay applications Nested clock trees are typical applications for the MPC9653. Designs using the MPC9653 as LVCMOS PLL fanout buffer with zero insertion delay will show significantly lower clock skew than clock distributions developed from CMOS fanout buffers. The external feedback option of the MPC9653 clock driver allows for its use as a zero delay buffer. The PLL aligns the feedback clock output edge with the clock input reference edge resulting a near zero delay through the device (the propagation delay through the device is virtually eliminated). The maximum insertion delay of the device in zero-delay applications is measured between the reference clock input and any output. This effective delay consists of the static phase offset, I/O jitter (phase or long-term jitter), feedback path delay and the output-to-output skew error relative to the feedback output.
Figure 3. VCC_PLL Power Supply Filter
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Calculation of part-to-part skew The MPC9653 zero delay buffer supports applications where critical clock signal timing can be maintained across several devices. If the reference clock inputs of two or more MPC9653 are connected together, the maximum overall timing uncertainty from the common PCLK input to any output is: I/O jitter confidence factor of 99.7% ( 3s) is assumed, resulting in a worst case timing uncertainty from input to any output of -197 ps to 297 ps (at 125 MHz reference frequency) relative to PCLK:
tSK(PP) = tSK(PP) =
[-17ps...117ps] + [-150ps...150ps] + [(10ps @ -3)...(10ps @ 3)] + tPD, LINE(FB) [-197ps...297ps] + tPD, LINE(FB)
tSK(PP) = t() + tSK(O) + tPD, LINE(FB) + tJIT()
CF
This maximum timing uncertainty consist of 4 components: static phase offset, output skew, feedback board trace delay and I/O (phase) jitter:
PCLKCommon
Due to the frequency dependence of the I/O jitter, Figure 5. "Max. I/O Jitter versus frequency" can be used for a more precise timing performance analysis.
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-t()
tPD,LINE(FB)
QFBDevice 1
tJIT()
Any QDevice 1
+tSK(O) +t()
QFBDevice2
tJIT()
Figure 5. Max. I/O Jitter versus frequency Driving Transmission Lines The MPC9653 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 20 the drivers can drive either parallel or series terminated transmission lines. For more information on transmission lines the reader is referred to Motorola application note AN1091. In most high performance clock networks point-to-point distribution of signals is the method of choice. In a point-to-point scheme either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50 resistance to VCC/2. This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC9653 clock driver. For the series terminated case however there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 6. "Single versus Dual Transmission Lines" illustrates an output driving a single series terminated line versus two series terminated lines in parallel. When taken to its extreme the fanout of the MPC9653 clock driver is effectively doubled due to its capability to drive multiple lines.
Any QDevice 2 Max. skew
+tSK(O) tSK(PP)
Figure 4. MPC9653 max. device-to-device skew Due to the statistical nature of I/O jitter a RMS value (1 s) is specified. I/O jitter numbers for other confidence factors (CF) can be derived from Table 10. Table 10: Confidence Factor CF
CF 1s 2s 3s 4s 5s 6s Probability of clock edge within the distribution 0.68268948 0.95449988 0.99730007 0.99993663 0.99999943 0.99999999
The feedback trace delay is determined by the board layout and can be used to fine-tune the effective delay through each device. In the following example calculation a
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MPC9653 OUTPUT BUFFER IN
14
3.0 OutA tD = 3.8956 OutB tD = 3.9386
2.5 RS = 36 ZO = 50 OutA VOLTAGE (V) 2.0
In 1.5
MPC9653 OUTPUT BUFFER IN
14
RS = 36
ZO = 50 OutB0
1.0
RS = 36
ZO = 50 OutB1
0.5
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0
Figure 6. Single versus Dual Transmission Lines The waveform plots in Figure 7. "Single versus Dual Line Termination Waveforms" show the simulation results of an output driving a single line versus two lines. In both cases the drive capability of the MPC9653 output buffer is more than sufficient to drive 50 transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the MPC9653. The output waveform in Figure 7. "Single versus Dual Line Termination Waveforms" shows a step in the waveform, this step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 36 series resistor plus the output impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: = VS ( Z0 / (RS+R0 +Z0)) = 50 || 50 = 36 || 36 = 14 = 3.0 ( 25 / (18+14+25) = 1.31V At the load end the voltage will double, due to the near unity reflection coefficient, to 2.6V. It will then increment towards the quiescent 3.0V in steps separated by one round trip delay (in this case 4.0ns). VL Z0 RS R0 VL
2
4
6
8 TIME (nS)
10
12
14
Figure 7. Single versus Dual Waveforms Since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines the situation in Figure 8. "Optimized Dual Line Termination" should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched.
MPC9653 OUTPUT BUFFER
14
RS = 22
ZO = 50
RS = 22
ZO = 50
14 + 22 k 22 = 50 k 50 25 = 25 Figure 8. Optimized Dual Line Termination
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MPC9653 DUT ZO = 50
Differential Pulse Generator Z = 50
ZO = 50
W
RT = 50 VTT
RT = 50 VTT
Figure 9. PCLK MPC9653 AC test reference
VCC VCC VCC VCC
B2 B2
GND
PCLK PCLK FB_IN
VPP = 0.8V
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VCMR = VCC-1.3V VCC VCC
GND tSK(O) The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device
B2
GND t(PD)
Figure 10. Output-to-output Skew tSK(O)
VCC VCC tP T0 DC = tP /T0 x 100% The time from the PLL controlled edge to the non controlled edge, divided by the time between PLL controlled edges, expressed as a percentage
Figure 11. Propagation delay (t(PD), static phase offset) test reference
PCLK
B2
GND FB_IN
TJIT() = |T0 -T1 mean| The deviation in t0 for a controlled edge with respect to a t0 mean in a random sample of cycles
Figure 12. Output Duty Cycle (DC)
Figure 13. I/O Jitter
TN
TN+1
TJIT(CC) = |TN -TN+1 |
T0
TJIT(PER) = |TN -1/f0 |
The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs
The deviation in cycle time of a signal with respect to the ideal period over a random sample of cycles
Figure 14. Cycle-to-cycle Jitter
Figure 15. Period Jitter
VCC=3.3V 2.4 0.55 tF tR
Figure 16. Output Transition Time Test Reference
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OUTLINE DIMENSIONS
FA SUFFIX LQFP PACKAGE CASE 873A-03 ISSUE B
4X
6 D1 D1/2
PIN 1 INDEX 32 25
0.20 H A-B D e/2 3 A, B, D
1
E1/2 A
B E
DETAIL G 8 17
F 4 F E/2 DETAIL G
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DATUMS A, B, AND D TO BE DETERMINED AT DATUM PLANE H. 4. DIMENSIONS D AND E TO BE DETERMINED AT SEATING PLANE C. 5. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED THE MAXIMUM b DIMENSION BY MORE THAN 0.08-mm. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD OR PROTRUSION: 0.07-mm. 6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25-mm PER SIDE. D1 AND E1 ARE MAXIMUM PLASTIC BODY SIZE DIMENSIONS INCLUDING MOLD MISMATCH. 7. EXACT SHAPE OF EACH CORNER IS OPTIONAL. 8. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.1-mm AND 0.25-mm FROM THE LEAD TIP.
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6 E1
7
9
D D 4
D/2
4X
0.20 C A-B D
H
SEATING PLANE
28X
e
32X
0.1 C
C
DETAIL AD
PLATING BASE METAL
b1 c
8X
( q1_)
R R2 R R1
A
A2
0.25
GAUGE PLANE
A1
(S) (L1) DETAIL AD
L
q_
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EEEE EEEE
b 0.20
M
c1
DIM A A1 A2 b b1 c c1 D D1 e E E1 L L1 1 R1 R2 S
5
8
C A-B D
SECTION F-F
MILLIMETERS MIN MAX 1.40 1.60 0.05 0.15 1.35 1.45 0.30 0.45 0.30 0.40 0.09 0.20 0.09 0.16 9.00 BSC 7.00 BSC 0.80 BSC 9.00 BSC 7.00 BSC 0.50 0.70 1.00 REF 0_ 7_ 12 _REF 0.08 0.20 0.08 --- 0.20 REF
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NOTES
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MPC9653
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E Motorola Inc. 2003
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